Measuring current, especially without undue interference in a circuit, can be problematic. The use of series resistors to measure a voltage drop corresponding to current creates a power loss of itself and can limit performance in a circuit. For example, in a class A/B amplifier circuit where rail-to-rail amplification is an important characteristic, the use of a resistor in series with the output drivers for measuring quiescent current may interfere with rail-to-rail operation.
Current measuring techniques are further complicated when the circuit under test is incorporated in a semiconductor. Probing a node internal to a semiconductor, even in a test environment, may be difficult or impossible, given fine line widths and chip passivation. Even when an internal node is successfully probed, the impedance of the probe itself is likely to alter the performance of the circuit under test.
Beyond current measurement issues, attempts to set a known quiescent current in a semiconductor integrated circuit can be complex due to variability that is difficult to predict or control. For example, in a class A/B amplifier circuit, quiescent current may be proportional to current through a biasing circuit, but even when gates in the bias and output driver circuits are drawn in a given W/L proportion, low activation voltages in the power output driver transistors may cause the W/L to shift significantly, and unpredictably, in the presence of quiescent bias voltages. Thus, the initial known relationship between the bias circuit and driver circuit becomes unknown and the quiescent current through the drivers is virtually impossible to predict over a range of operating voltages and semiconductor process variability.
FIG. 1 illustrates a prior art embodiment of a class A/B amplifier. In the following discussion, transistors designated MP are PMOS devices and transistors designated MN are NMOS devices. Class A/B amplifiers are widely used in circuits that need to minimize cross-over distortion, such as audio amplifiers and voice coil motors (VCM) in hard disc drives. Two characteristics make class A/B amplifiers very popular. The first characteristic is low cross-over distortion, that is, a smooth transition from negative voltage to positive voltage. The second characteristic is rail-to-rail output driving capability, i.e. the output can drive from very nearly VDD to very nearly ground. To realize both high drive capability and low cross-over distortion, the quiescent current, that is, standby current with no output signal present, should be well defined. Therefore, it is important to detect and control the quiescent current accurately in class A/B amplifier design.
The circuit 100 of FIG. 1 is suitable for use in driving a load 102 such as a VCM. The V+ and V− inputs differentially drive buffer circuits MN1/MN2/MN3/MN4 and MP3/MP4/MP7/MP8. The buffer circuit outputs on drive nodes ngate and pgate drive the gates of power transistors MN0 and MP0, respectively. When sourcing current, Ip, through load 102, current through output driver MP0 is Iq+Ip. When sinking current, In, from load 102, current through the output driver MN0 is Iq+In. When there is no current through the load 102, the current through both MP0 and MN0 is Iq. The total quiescent current of the circuit 100 is slightly more than the quiescent current through transistors MP0 and MN0, but the difference is negligible and is not included in this discussion. Quiescent current (Iq) is set by matching transistor pairs MN9/MN0 and MP9/MP0 and matching bias currents Ibias 202 and Ibias 204, according to the formula:
      I    q    =                    I        bias            ⁢                                    (                          W              /              L                        )                                MP            ⁢                                                  ⁢            0                                                (                          W              /              L                        )                                MP            ⁢                                                  ⁢            9                                =                  I        bias            ⁢                                    (                          W              /              L                        )                                MN            ⁢                                                  ⁢            0                                                (                          W              /              L                        )                                MN            ⁢                                                  ⁢            9                              
In one exemplary embodiment, Ibias is set to 20 uA and the W/L ratio (ratio of gate width to length, roughly equivalent to gain) is 100. Quiescent current is then:Iq=20 uA*100=2 mA.
The feedback loop through MP5/MP6 keep the gate of MP9 at the same voltage as the gate of MP0 since both pgate and n8 are one diode drop above pbias. Similarly, the feedback loop through MN5/MN7 keep the gate of MN9 at the same voltage as the gate of MN0 because both ngate and n7 are one diode drop below nbias. MN0 and MP0 are drawn with minimum channel lengths to reduce on resistance and increase performance of the output. However, minimum channel length devices are susceptible to channel length narrowing due to Vds voltage. When MN0 and MP0 have high Vds voltages compared to MN9 and MP9, an effective W/L mismatch may develop, causing quiescent current to vary from the design goal. For example, in a typical application, VDD may be 12V and with no load current, the voltage at Aout will be 6 volts. The 6 volt Vds can cause a mismatch between the effective W/L of MN0 and MP0 compared to the W/L of their respective paired transistors MN9 and MP9, making quiescent current difficult, if not impossible, to predict. Process variation and temperature can further exaggerate this effect.
Table 1 shows a range of quiescent current in a class AB driver stage over representative process corners for a single set of ideal conditions of Iq_ideal=2 mA, VDD=12V, Aout=6V.
TABLE 1Corner/Temp−2025125TT4.49 mA4.43 mA4.39 mASS3.24 mA3.26 mA3.31 mAFF8.53 mA8.05 mA7.36 mA
In spite of this variability, it is often desirable, if not crucial, to set quiescent current to a known value. For example, in a class A/B amplifier circuit, optimal drive and crossover distortion may be achieved only when quiescent current is tightly controlled. In order to control quiescent current, it first must be accurately measured.